1. Technical Field
The present invention generally relates to testing of integrated circuits (ICs). More specifically to testing of ICs having programmable functions, programmable interconnections, and one or more embedded devices.
2. Related Art
Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs) and microprocessors circuits are known, and have been used, according to performance requirements for a given circuit. For example, microprocessors are often preferred when flexibility and variable control are key design considerations. On the other hand, ASICs are often selected when performance or small circuit size is essential. FPGAs are often used when programmability and performance are important. Heretofore, however, FPGAs have typically been made to include only selectable logic blocks and have not included designs for robust processing of data. FPGAs have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, etc.
FIG. 1 illustrates a generic schematic block diagram of an FPGA 110. The FPGA 110 includes configurable logic fabric 112 (containing programmable logic gates and programmable interconnects) and configurable input/output blocks 114. The configurable input/output blocks 114 are fabricated on the perimeter of a substrate supporting the FPGA 110 and coupling to the pins of the integrated circuit to allow access to the configurable logic fabric 112.
The logic fabric 112 may be configured to perform a wide variety of functions corresponding to particular end user applications. For example, the configurable logic fabric 112 may be configured in a symmetric array arrangement, a row-based arrangement, a column based arrangement, a hierarchical programmable logic device arrangement, or a sea-of-gates arrangement, each having different functional advantages.
FIG. 2 illustrates the logic fabric 112 configured in a symmetrical array arrangement. Each logic block 216 of a plurality of logic blocks 216 is configured (usually by the end user) as an array of rows and columns to perform a specific logic function. More complex logic functions may be obtained by interconnecting individually configured logic blocks using a plurality of programmable interconnections 218. Accordingly, programmable interconnections 218 are formed between each of the logic blocks of each row and each column.
Programmable interconnections 218 also provide selective connectivity between each logic block of the array of logic blocks 216 and the configurable input/output blocks 114. Programmable interconnections 218 may be formed using static random access memory (RAM) cell technology, anti-fuse cell technology, EPROM transistor technology, and/or EEPROM transistor technology. If the FPGA utilizes static RAM programmable connections, the connections are made using pass transistors, transmission gates, and/or isolation circuits that are controlled by the static RAM cells.
If the FPGA utilizes anti-fuse interconnections, the interconnections typically reside in a high impedance state and can be configured into a low impedance state, or fused state, to provide the selective connectivity. If the FPGA utilizes EPROM or EEPROM based interconnections, the interconnection cells may be configured, thus allowing the FPGA to be reconfigured.
FIG. 3 illustrates a schematic block diagram of the configurable logic fabric 112 being implemented in a row-based arrangement. In this configuration, the logic fabric 112 includes a plurality of logic blocks 216 arranged in rows. Between each row of the logic blocks are programmable interconnections 218. Programmable interconnections 218 may be implemented utilizing static RAMS, dynamic RAMS and NVRAM, EPROM technology, and/or EEPROM technology.
FIG. 4 illustrates a schematic block diagram of the logic fabric 112 being configured in a sea-of-gates configuration. The logic blocks and programmable interconnections are substantially similar to that described above.
FIG. 5 illustrates the configurable logic fabric 112 being implemented as a hierarchical logic device. In this implementation, the configurable logic fabric 112 includes logic device blocks 522 and programmable interconnections 218. As shown, four logic device blocks 522 are in the corners with an interconnect 218 in the middle of the logic device blocks. In addition, the interconnects include lines coupling the configurable logic device blocks 522 to the interconnect 218. As such, the logic device blocks 522 may be configured to operate singularly or in combination with other logic blocks 522 according to the programming of the programmable interconnections 218.
As is known, field programmable gate arrays offer the end user the flexibility of implementing custom integrated circuits while avoiding the initial cost, time delay and inherent risk of application specific integrated circuits (ASIC). They also provide a degree of hardware-based customization that does not require custom application-specific designs, such as ASICs.
While FPGAs have these advantages, there are some disadvantages. For instance, an FPGA configured to perform a similar function as implemented in an ASIC, sometimes can require significantly more die area than the ASIC. The manufacturing expense of an FPGA, therefore, is greater than that of an ASIC. Additionally, FPGA performance is sometimes lower than that of an ASIC.
To mitigate some of the disadvantages of FPGAs with respect to ASICs, some FPGA manufacturers are including ASIC-like functions on the same substrate as the configurable logic fabric. For example, FPGAs are now commercially available that include RAM blocks and/or multipliers in the configurable logic fabric 112. As such, the logic fabric 112 does not have to be configured to perform RAM functions and/or multiplier functions when such functions are needed. Thus, for these functions, significantly less die area is needed within the FPGA.
There are designs presently being developed to incorporate embedded microprocessors and other similar and known devices into an FPGA fabric by the present Assignee. As these designs mature, there will exist a need to provide for testing of the devices in a manner that enables one to determine whether the FPGA is formed and operating correctly, as well as, the processor or other device that is embedded there within.
Testers for testing integrated circuits are well known. Typically, a tester has local sequencers, each of which is programmable to establish operational logic states or a specified set of electrical conditions so that, with the input of data, an expected output may be compared to an actual output to determine proper operation of the device under test (DUT). In such systems, each local sequencer generates input data signals (events) for the DUT with reference to a global clock or other reference signals. Typically, sequencers are arranged and formed to present multiple test vectors to the (DUT). The sequencers further include memory and processing logic to provide the test vectors for testing the device.
Testers provide stimulus patterns for the DUT to prompt it to produce an expected output result with respect to the data transmitted to it for evaluation. Thereafter, the expected output is compared to an actual output to determine whether the DUT passed the test. In addition to testers, the use of scan latches to emulate pin connections is generally known. The scan latches are loaded with test signals prior to a clock pulse being generated to prompt the device to process the information stored in the scan latches. A discussion of this technology in general terms may be found in the text Abramovici, Breuer and Friedman, Digital System Testing and Testable Design, (IEEE 1990).
The foregoing discussion of test vectors and test data patterns relates to devices for which pin access is not a problem. In an environment in which the device under test is embedded in a system, such as an FPGA fabric, providing stimulus patterns are not an achievable task without significant and, perhaps, unreliable, manipulation of the surrounding circuitry to produce the desired stimulus patterns and data inputs for testing the device. Accordingly, it is difficult to reliably and relatively easily provide the test vectors and test data to embedded devices within an FPGA fabric as part of running known test procedures.
What is needed, therefore, is a method and apparatus that enables one to test specific circuit components embedded within an FPGA by providing signals and measuring responses there from.